Computer Science (9645) | The Fetch-Execute cycle and interrupts

🧠 Chapter 3.7.3: The Fetch-Execute Cycle and Interrupts

Hello! Welcome to the heart of Computer Science. This chapter explains the fundamental process that makes a computer *a computer*. Every single instruction your machine runs—from loading a webpage to typing a single letter—must go through this cycle. If you understand this, you understand how the Central Processing Unit (CPU) truly works!

Don't worry if the registers sound like complicated names at first. We will break down this complex process into simple, manageable steps, using analogies to help it stick!

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1. The Fetch-Execute Cycle (FEC): The CPU's Routine

The Fetch-Execute Cycle (FEC) is the continuous process carried out by the processor (CPU) to execute machine code programs stored in main memory. It's often called the Instruction Cycle.

1.1 Essential Registers (The CPU's Tools)

Before diving into the cycle, we need to quickly review the dedicated registers involved (these are small, super-fast memory locations inside the CPU itself).

• Program Counter (PC): Stores the memory address of the next instruction to be executed. (*Think of this as the bookmark in the recipe book.*)
• Memory Address Register (MAR): Stores the memory address currently being accessed (either for reading or writing).
• Memory Buffer Register (MBR): Temporarily holds the data or instruction that has just been fetched from, or is about to be written to, memory. (Also known as the Memory Data Register/MDR.)
• Current Instruction Register (CIR): Stores the machine code instruction currently being decoded and executed.
• Status Register (SR): Holds flags (bits) that indicate the current state of the CPU, such as whether a calculation resulted in an overflow or a zero value.

1.2 The Three Stages of the Fetch-Execute Cycle

The cycle consists of three core stages: Fetch, Decode, and Execute.

Stage 1: FETCH

This stage retrieves the next instruction from main memory.

1. The address of the next instruction is copied from the Program Counter (PC) to the Memory Address Register (MAR).
   (PC → MAR)
2. The address in the MAR is sent via the Address Bus to main memory.
3. The Control Unit sends a READ signal along the Control Bus.
4. The instruction located at that address is retrieved from main memory and travels back to the CPU via the Data Bus, arriving in the Memory Buffer Register (MBR).
5. The content of the MBR (the instruction) is copied to the Current Instruction Register (CIR).
   (MBR → CIR)
6. The Program Counter (PC) is automatically incremented to point to the address of the next instruction in the program sequence.

Stage 2: DECODE

The Control Unit figures out what the instruction means.

• The instruction in the CIR is split into two parts: the Opcode (what to do, e.g., ADD, LOAD) and the Operand (what data or address to use).
• The Control Unit interprets the opcode and prepares the necessary hardware components (like the ALU or other registers) to carry out the action.
• If the instruction involves data from memory (e.g., LOAD R1, [Address]), the Control Unit uses the address part of the instruction to fetch the required data into the MBR, ready for the next stage.

Stage 3: EXECUTE

The instruction is carried out.

• The Control Unit generates the specific control signals required to perform the action.
• If the instruction is an arithmetic or logic operation (like ADD or AND), the Arithmetic Logic Unit (ALU) performs the calculation using data often stored in the General-Purpose Registers.
• If the instruction is a branch (jump), the address specified in the instruction is loaded directly into the Program Counter (PC), changing the flow of the program.
• After execution, the CPU checks for Interrupts (see Section 2) before restarting the cycle.

Key Takeaway: The CPU's Job

The FEC is the continuous loop of fetching instructions, understanding them, and then performing the required operation. This serial execution of machine code is the definition of the Stored Program Concept.

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2. Interrupts: Stopping the Cycle for Emergencies

Normally, the CPU executes instructions happily, one after the other. But what happens if the printer runs out of paper, or the network card receives a high-priority packet? The CPU needs a way to stop what it's doing and handle the urgent situation.

2.1 What is an Interrupt?

A Interrupt is a signal, generated by hardware or software, that indicates an event requiring immediate attention from the CPU.

Analogy: Imagine the CPU is a baker following a recipe (the program). An interrupt is the fire alarm going off. The baker must stop mid-step, deal with the emergency, and then come back to the exact point in the recipe where they left off.

2.2 The Role of Interrupt Service Routines (ISRs)

• When an interrupt occurs, the CPU must execute a small, dedicated program designed to handle that specific event. This is called an Interrupt Service Routine (ISR), or sometimes an interrupt handler.
• The ISR deals with the cause of the interrupt (e.g., communicating with the faulty device, managing disk I/O, or dealing with an error).

2.3 Effect of Interrupts on the Fetch-Execute Cycle

The CPU checks for interrupts right at the end of the Execute stage, before starting the next Fetch.

If an Interrupt is detected:

1. Pause: The CPU pauses the currently running program.
2. Save Volatile Environment: This is the crucial step! The CPU must save the state of the registers that hold temporary information about the current program, so it can resume exactly where it left off.
3. Service the Interrupt: The CPU loads the starting address of the appropriate ISR into the Program Counter (PC), and the ISR begins execution.
4. Restore: Once the ISR finishes, the saved register values are restored from the Stack back into the CPU registers.
5. Resume: The CPU returns to the main program and restarts the Fetch cycle from the instruction address retrieved from the restored PC.

Saving the Volatile Environment

The volatile environment refers to the temporary data and state information held in the CPU registers that would be overwritten if the ISR ran without saving them. This environment must be saved, usually onto a dedicated area of main memory called the Stack.

The volatile environment includes:

• The Program Counter (PC): Essential for knowing the return address.
• The Status Register (SR): Contains important flags (like overflow or zero status).
• The Stack Pointer: Needed if the ISR itself uses the stack.
• Any other General-Purpose Registers that the ISR might alter.

Key Takeaway: Control and Efficiency

Interrupts allow the CPU to manage inputs, outputs, and errors efficiently without constantly having to check (or "poll") every device. This ability to handle urgent external events is a core function of the Operating System's interrupt handling role.