Computer Science (9645) | Internal hardware components of a computer

👋 Welcome to the Machine's Guts!

Hi everyone! This chapter, Internal hardware components of a computer, is the core foundation of Computer Organisation and Architecture. Don't worry if all the acronyms (ALU, MAR, MBR!) look intimidating—we'll break them down step-by-step.
Understanding these components is like looking inside a supercar's engine. Once you know how the parts connect and communicate, you'll understand exactly how the computer executes every instruction you give it. Let’s get started!

3.7.1 Basic Internal Components

A computer system is made up of several key internal components that work together in a coordinated way to process information.

The Key Players (Components)

• Processor (CPU): The "brain" of the computer. It executes instructions and manages the flow of data.
• Main Memory (RAM): This is temporary, fast storage used to hold the programs and data currently being used by the CPU.
• I/O Controllers: These are special chips that act as intermediaries, managing communication between the CPU and peripherals (like keyboards, printers, or disk drives).

The Communication System: Buses

Components need to communicate constantly. They do this using collections of parallel wires called Buses. Think of buses as the highways connecting different parts of the computer city.

There are three main types of bus, each with a specific job:

1. The Address Bus

The Address Bus carries the memory location (or address) of the data the CPU wants to read or write.
Analogy: This is like the postal code or street address. It specifies the destination.

• It is unidirectional (data flows one way: from the CPU to the memory/I/O controller).
• The width of the address bus determines the maximum addressable memory capacity (how many unique memory locations the CPU can access).
  • If an address bus has \(n\) lines (bits), it can access \(2^n\) addresses.
  • Example: A 32-bit address bus can access \(2^{32}\) bytes (4 Gigabytes) of memory.

2. The Data Bus

The Data Bus carries the actual data or instruction being moved between the CPU and main memory or I/O controllers.

• It is bidirectional (data flows both ways: to and from the CPU).
• The width of the data bus (known as the word length or data bus width) determines how many bits the CPU can process or move in a single operation.

3. The Control Bus

The Control Bus carries control signals (commands) from the CPU to coordinate and manage all activities.

• It is bidirectional (carrying signals like "Read" or "Write" commands from the CPU, and status signals like "Ready" from other components).
• Example: A "Memory Write" signal tells the main memory to accept the data currently on the Data Bus and store it at the address currently on the Address Bus.

3.7.2 The Processor and its Components

The processor (CPU) is built from several key functional units and small, high-speed storage locations called registers.

The Functional Units

• Arithmetic Logic Unit (ALU): Performs all arithmetic calculations (like addition, subtraction) and logical operations (like AND, OR, NOT, comparisons).
• Control Unit (CU): Manages the entire CPU operation. It decodes instructions, controls the flow of data between the CPU and other devices, and sends timing and control signals via the Control Bus.
• Clock: Provides timing signals (pulses) that synchronise all the operations within the CPU and other components. Each pulse signals the start of a new operation.

Registers: High-Speed Temporary Storage

Registers are small, extremely fast memory locations within the CPU itself. They hold temporary values needed during the Fetch-Execute cycle.

Dedicated Registers (The Specialists)

These have specific, fixed roles:

1. Program Counter (PC): Stores the address of the next instruction to be fetched from memory. (It’s always pointing ahead!)
2. Current Instruction Register (CIR): Stores the instruction that is currently being decoded and executed.
3. Memory Address Register (MAR): Stores the memory address of the data or instruction that the CPU wants to access (read from or write to).
4. Memory Buffer Register (MBR) (also known as Memory Data Register, MDR): Temporarily holds the data or instruction that has just been fetched from memory, or data waiting to be stored into memory.
5. Status Register (SR): Contains flags (individual bits) set by the ALU after an operation, indicating conditions such as whether the result was zero, whether an overflow occurred, or if an interrupt is pending.

There are also General-Purpose Registers which are used by programmers to temporarily store data values during calculations, reducing the need to access main memory.

3.7.3 The Fetch-Execute Cycle and Interrupts

The Stored Program Concept states that machine code instructions (the program) are stored in main memory and are fetched and executed serially by the processor, which performs arithmetic and logical operations.
The continuous cycle the CPU follows to carry out this stored program is the Fetch-Execute Cycle.

The Fetch-Execute Cycle (The Continuous Loop)

Phase 1: Fetch

The goal is to get the next instruction from memory.

1. The address in the PC is copied to the MAR.
2. The PC is incremented (usually by 1, ready for the next instruction).
3. The instruction stored at the address in the MAR is fetched from memory via the Data Bus and temporarily stored in the MBR. (The Control Bus issues the "Read" command).
4. The instruction in the MBR is copied into the CIR.

Phase 2: Decode

The Control Unit looks at the instruction in the CIR and interprets it.

It determines: What operation needs to be performed? And where is the data (operand) needed for that operation? The CU then prepares the necessary control signals.

Phase 3: Execute

The instruction is carried out.

• If the instruction is an arithmetic/logic operation, the ALU performs it.
• If it involves accessing memory (loading or storing data), the MAR and MBR are used again.
• The Status Register (SR) is updated based on the result of the execution.

Once executed, the cycle starts again, fetching the instruction now pointed to by the PC.

Interrupts: Handling Unexpected Events

An Interrupt is a signal sent to the CPU that halts the current process and causes it to switch to another task (usually a higher priority one).

Did you know? Interrupts are essential! Without them, your CPU would have to constantly stop its main job to check if the mouse moved, which is highly inefficient.

The Role of Interrupts and ISRs

• Interrupts are generated by hardware (e.g., I/O controllers when a printer finishes a job) or software (e.g., an error like dividing by zero).
• After the Execute stage, the CPU checks the Status Register (SR) to see if any interrupts are pending.
• If an interrupt occurs, the CPU halts the current Fetch-Execute cycle and services the interrupt using an Interrupt Service Routine (ISR).

Saving the Volatile Environment (Context Switching)

Before running the ISR, the CPU must save the state of the task it was interrupted from. This saved information is called the volatile environment (or context) and is usually pushed onto a stack in main memory.

The volatile environment includes:

• The current value of the Program Counter (PC) (the return address, so the CPU knows where to go back to).
• The contents of the Status Register (SR).
• The contents of any other dedicated registers that might be altered by the ISR (like MAR, MBR, CIR).

Once the ISR is complete, the volatile environment is restored (popped off the stack), and the CPU resumes the original program from the saved return address.

3.7.1 & 3.7.2 Architectural Models

There are two main ways computer scientists design the relationship between the processor and memory, especially concerning how instructions and data are handled.

1. Von Neumann Architecture

This is the traditional and most common model (used in typical desktop PCs).

• It uses a single shared memory space for both data and instructions.
• It uses a single bus system (Address Bus, Data Bus, Control Bus) to transfer both data and instructions between the CPU and memory.
• Advantage: It's simpler to design and manage. Memory capacity is used efficiently.
• Disadvantage: It suffers from the Von Neumann Bottleneck—because the same bus is used for everything, the CPU can only fetch an instruction *or* fetch/store data at any one time, slowing down execution speed.

2. Harvard Architecture

This architecture separates the memory and bus paths.

• It uses separate memory spaces for instructions and data.
• It uses separate bus systems for instruction transfers and data transfers.
• Advantage: The CPU can fetch an instruction and access data simultaneously (at the same time), which greatly improves speed and allows for pipelining (starting the next fetch while the current instruction executes).
• Disadvantage: More complex hardware; memory is less flexible (you have to pre-allocate space specifically for instructions and specifically for data).

In practice, modern, high-performance processors often use a modified Harvard architecture internally (especially for cache memory) to gain speed advantages, while still appearing externally as a Von Neumann machine.

3.7.4 Factors Affecting Processor Performance

Not all CPUs are created equal! Several factors influence how fast and efficiently a processor can run programs.

1. Clock Speed

This is the rate at which the clock generates pulses, measured in Hertz (Hz) (e.g., 3.0 GHz).

• Effect: A higher clock speed means more Fetch-Execute cycles can be completed per second, leading to faster processing.

2. Multiple Cores

A core is essentially an independent processing unit (its own ALU, CU, and registers).

• Effect: More cores allow the processor to execute multiple instructions simultaneously (parallel processing), which significantly speeds up performance for multitasking or running specially designed programs.

3. Cache Memory

This is a small amount of extremely fast memory located either directly on the CPU chip (L1, L2) or very close to it (L3).

• Effect: Cache stores frequently accessed data and instructions. If the CPU finds what it needs in the cache (a "cache hit"), it avoids the much slower access to main memory, dramatically improving speed.

4. Word Length and Bus Widths

Word length refers to the number of bits the CPU processes at once (e.g., 32-bit or 64-bit systems).

• Data Bus Width: A wider Data Bus (e.g., 64 bits instead of 32 bits) allows more data to be transferred between the CPU and memory in one clock cycle. More lanes on the highway = faster traffic flow.
• Address Bus Width: A wider Address Bus means the CPU can access a much larger range of memory locations.

3.7.5 Secondary Storage

While Main Memory (RAM) is fast, it is volatile—it loses all its data when the power is off. We need Secondary Storage to permanently keep our programs, files, and operating system when the computer is shut down.

Characteristics and Devices

1. Magnetic Hard Disk (HDD)

Principle of Operation: Stores data magnetically on spinning metal platters. A read/write head floats just above the platter surface to change or detect magnetic polarity (representing 1s and 0s).

• Purpose: High capacity, cost-effective storage for bulk data and backups.
• Main Characteristic: Contains moving mechanical parts (platters, arms, heads), making them vulnerable to physical shock and slower to access data.

2. Solid-State Drive (SSD)

Principle of Operation: Stores data electronically using flash memory (like large USB sticks). Data is stored in electrical circuits without any moving parts.

• Purpose: Fast boot-up, high-speed program loading, and general system responsiveness.
• Main Characteristics: Much faster access times than HDDs, silent operation, high resilience to shock, but generally more expensive per Gigabyte.

3. Cloud Storage

Definition: Cloud storage is data stored on servers located at a remote location (often large data centres) that is accessed via the Internet.

• Advantages over Local Storage: Data can be accessed from any location/device; easier backup/recovery; scalability (buy as much space as you need).
• Disadvantages over Local Storage: Requires an Internet connection; speed depends on connection quality (latency); security and privacy concerns (data stored by a third party).

Don't worry if this feels like a lot of detail! Remember that everything works together in a beautiful, fast cycle. Focus on the job of each component—if you know what the MAR *does* (holds an address), you can easily trace the Fetch cycle! Keep reviewing these key roles, and you'll master this section. Good luck!